| Title |
Simulation of the MOS transistors structures channel technological problems / |
| Translation of Title |
MOS tranzistorinių struktūrų kanalo technologinių problemų modeliavimas. |
| Authors |
Kašauskas, V ; Anilionis, R ; Eidukas, D |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2010, Nr. 10, p. 139-142.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
The MOS transistor channel structure depends on a number of technological processes. The main problem includes the channel shortening by applying additional impurity distributions in the source and drain areas, using the ion implantation technological operations (TO). In the process it is important to know and accurately determine the right ion implantation TO technological modes. During the simulation we identified the TO critical modes, distorting or breaking down the channel, of the drain and source area formation. Effects of ion implantation TO modes to the transistor output characteristics was identified. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2010 |
| CC license |
|
