| Title |
Tunable pseudocapacitance fractional-order capacitor integrated in a 65 nm CMOS process |
| Authors |
Sotner, Roman ; Jerabek, Jan ; Polak, Ladislav ; Kubanek, David ; Kledrowetz, Vilem ; Theumer, Radek ; Andriukaitis, Darius ; Shadrin, Alexandr ; Dvorak, Jan ; Semenov, Dmitrii ; Horsky, Pavel |
| DOI |
10.1016/j.rineng.2026.111469 |
| Full Text |
|
| Is Part of |
Results in engineering.. Amsterdam : Elsevier. 2026, vol. 31, art. no. 111469, p. 1-14.. ISSN 2590-1230 |
| Keywords [eng] |
Adjustability ; Bias adjustment ; CMOS ; Dual control ; Fractional order ; Pseudocapacitance |
| Abstract [eng] |
This work presents a novel integrated design of a fractional-order capacitor of order 0.5 with an adjustable pseudocapacitance controlled by a DC bias voltage. The device was fabricated using the 65 nm TSMC CMOS process. The pseudocapacitance can be adjusted in the range from 39 to 87 nF/ sec ^0.5 by applying a serial DC bias voltage at the input terminal (from 0 up to 0.7 V), and from 39 to 57 nF/ sec ^0.5 by adjusting the bulk-source voltage (from 0 up to 0.9 V) available at an independent terminal. The maximum error of adjustment between the simulated and measured responses is 12%. The first tuning approach is advantageous for remote adjustment of specific applications from a preceding stage within the signal-processing chain, where the signal source itself provides the required DC control component. The operational frequency range spans two decades. The operational frequency bandwidth ranges approximately from 2 kHz to >500 kHz, varying with DC driving. Signal amplitudes up to 100–200 mV can be processed linearly without introducing significant distortion. Process-corner and temperature variation (from −40 °C to +40 °C) analyses indicate maximum parameter deviations of up to 10%. The size of the chip is comparable to that of common SMT components, with a cell layout area of 0.911×0.162 mm (0.148 mm2). The application example of the electronically fractional-order RLC low-pass filter is presented, demonstrating a slope of -30 dB/dec and pole frequency adjustability between 22 kHz and 13 kHz through electronic tunability of the designed CPE. |
| Published |
Amsterdam : Elsevier |
| Type |
Journal article |
| Language |
English |
| Publication date |
2026 |
| CC license |
|