| Title |
Functional delay clock fault models |
| Another Title |
Funkciniai sinchroniniai vėlinimo gedimų modeliai. |
| Authors |
Bareiša, Eduardas ; Jusas, Vacius ; Motiejūnas, Kęstutis ; Šeinauskas, Rimantas |
| Full Text |
|
| Is Part of |
Informacinės technologijos ir valdymas = Information technology and control.. Kaunas : Technologija. 2008, t. 37, Nr. 1, p. 12-18.. ISSN 1392-124X. eISSN 2335-884X |
| Abstract [eng] |
The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is the choice of the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault models for synchronous sequential circuits: functional clock at-speed, functional clock static-based and functional clock delay. The introduced models are based on the primary input values, on the primary output values and on the state bits values of the programming prototype. The presented experimental results explore the possibilities of the functional test that is constructed on the base of the static-based fault model to detect the transition and stuck-at faults. The fault coverage of the functional static-based, stuck-at and transition faults corresponds with one another quite well. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2008 |
| CC license |
|
