| Title |
The transition fault model of programmable logic / |
| Another Title |
Programuojamųjų loginių lustų perjungimo gedimų modelis. |
| Authors |
Abraitis, V ; Tamoševičius, Ž |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2008, Nr. 1, p. 73-76.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
There is presented the fault model of programmable integrated circuits in this paper, when programmable integrated circuits are configured to implement a given application. Proposed fault model can be used with traditionally automatic test sequence generators and result will be exhaustive test of transition faults for programmable integrated circuits with given configuration. Model was tested using Virtex family PFGAs. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2008 |
| CC license |
|
