| Title |
Specific features of faults of combinational CMOS circuits / |
| Another Title |
KMOP kombinacijų schemų gedimų diagnostikos ypatumai. |
| Authors |
Benisevičiūtė, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2006, Nr. 6, p. 83-86.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
This research work investigated a problem of application of transistors level fault model and its adequacy to faults at logical level of circuit. There were elaborated the faults at logical and at functional level using the software package CADENCE. The faults at transistors level were simulated by software package PSPICE. There were done the comparative results of fault simulation and fault coverage at transistors level and at logical level of CMOS circuit. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2006 |
| CC license |
|
