| Title |
Save testuojančių schemų testavimas / |
| Another Title |
Testing of BIST Circuits. |
| Authors |
Tamoševičius, Ž |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2005, Nr. 7, p. 79-83.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
Delay testing of combinational logic in a clocked environment is analyzed. A model based upon paths is introduced for delay faults. Any path with a total delay exceeding the clock interval is called a “path fault”. This is global delay fault model because it is associated with an entire path under test. The more familiar slow – to rise or slow – to – fall gate delay, on the other hand, is a local fault model. A procedure is described which identifies paths which are tested for path faults by a set of patterns. It does not involve delay simulation. The paths so identified are tested for path faults independent of the delays of any individual gate of the network. The number of properties related to path faults are described in this paper too. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
Lithuanian |
| Publication date |
2005 |
| CC license |
|
