| Title |
CMOS technologijos, maskuojant silicio nitridu, kokybė / |
| Another Title |
The analysis of quality of CMOS technology, covered by silicon nitride. |
| Authors |
Anilionis, R ; Andriukaitis, D ; Keršys, T |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2005, Nr. 4, p. 73-76.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
Problems of technology LOCOS, related with oxidation time, temperature, silicon oxide layer, patterned silicon nitride in CMOS structure was researched. During LOCOS most CMOS quality depend on gate channel shortening, diffusion region separation. LOCOS CMOS mathematical models are created using program SUPREM. It is determined, that most acceptable results are received when time t=360 min., temperature T=1000ºC, SiO2 thickness = 0,02 µm., Si3N4 thickness = 0,1 µm. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
Lithuanian |
| Publication date |
2005 |
| CC license |
|
