| Title |
Testing of FPGA logic cells / |
| Another Title |
FPGA loginių ląstelių testavimas. |
| Authors |
Bareiša, E ; Jusas, V ; Motiejūnas, K ; Šeinauskas, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2004, Nr. 7, p. 37-42.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
The manufacturing test procedure of RAM-based FPGAs uses several configurations and the exhaustive testing of all configurable logic blocks (CLB). The transformation of the circuit is applied during a test pattern generation. A multiplexer is added to every logic cell in such a way that it does not change a function of the circuit. The stuck-at faults are injected only on the data inputs of the multiplexer. Such an approach allows to use a classical gate level test pattern generator and ensures an exhaustive testing of every logic cell. The proposed approach was used to generate test sets for ISCAS85 benchmarks that were mapped into FPGA. We also conducted fault simulation experiments that show exhaustive test patterns are effective in detecting faults of different implementations of the same circuit. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2004 |
| CC license |
|
