| Title |
Testų išsamumo užtikrinimas save testuojančiose skaitmeninėse schemose / |
| Another Title |
Full fault coverage in BIST circuit. |
| Authors |
Jusas, V ; Tamoševičius, Ž ; Benisevičiūtė, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2004, N. 1, p. 56-61.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
The paper describes the most important elements for test performing in built-in-self-test circuit: linear feedback shift register and multiple-input signature register. The paper analyses the basic methods of using shift registers in built-in-self-test circuit. The paper presents a new combined method for built-in self test circuit. The combined method is a combination of pseudo random and deterministic test patterns generation. The main point of the new method – enabling to add deterministic test patterns into a sequence of pseudo random test. There are used decoder and correction logic. Test generation and signature analysis are done on BILBO register, which enables to perform both function on single device. Presented method enables to reach 100% of test efficiency and minimize the quantity of hardware. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2004 |
| CC license |
|
