| Abstract [eng] |
Time interval measurement is a classical task of electronic measurements. However, achievement of high-resolution and low power in Time to Digital Converter (TDC) is still a challenge. This paper focuses on the implementation of TDC using Altera Cyclone family FPGA devices and on investigation of its timing characteristics and power consumption optimization. In this thesis Altera Quartus FPGA design platform was used. Altera embedded logic analyzer Signal Tap2 was used for experimental measurement of timing characteristics. Power consumption estimation was carried out using external power analyzer Yokogawa WT310 and power simulator PowerPlay Power Analyzer from Altera development environment. TDC features were examined using their synthesized implementations in Altera FPGA families Cyclone II, Cyclone III and Cyclone V. Nutt type TDC with 2.7 ns resolution was implemented using Altera FPGA. To generate high frequency reference signal ring oscillator (RO) was used, which determines TDC time measurement resolution. By increasing the gate number in RO, the generated signal period increases linearly. Changing FPGA design synthesis and assembly settings had little impact on RO period. Dynamic power of TDC hyperbolically decreases, when increasing the RO gate number. TDC power consumption was optimized by changing low frequency reference clock period. In this thesis it was shown that there exists the frequency of low speed reference clock, which corresponds to the minimum power consumption. It is also noted that the optimal low speed reference clock period depends on the measured time interval. Therefore, it is not possible to find the optimum low speed reference clock period in the whole range of measured time intervals. Thus, during designing of TDC, the expected range of measured intervals has to be considered as an important factor in order to minimize power consumption. |
