| Title |
Research on machine learning algorithm acceleration using FPGAs / |
| Translation of Title |
Mašininio mokymosi algoritmų spartinimo su programuojama logika tyrimas. |
| Authors |
Stasytis, Lukas |
| Full Text |
|
| Pages |
45 |
| Keywords [eng] |
machine learning ; FPGA ; CORDIC ; accelerator ; SVD |
| Abstract [eng] |
With recent advances in machine learning (ML) and a rapidly accelerating new frontier of digital logic design tooling for Field-Programmable Gate Array (FPGA) development, new opportunities exist for exploring the use of FPGAs in the ML field. In this work, the current state of the art digital logic design tool-chains and their use in the field of ML is explored and a design methodology is proposed for efficiently utilizing FPGAs as accelerators for compute-intense ML tasks. An FPGA prototype design for accelerating the Singular Value Decomposition (SVD) algorithm as well as the QR decomposition using the Coordinate Rotational Computer (CORDIC) as an abstraction layer arithmetic core is presented and analyzed with emphasis on DSP utilization. |
| Dissertation Institution |
Kauno technologijos universitetas. |
| Type |
Master thesis |
| Language |
English |
| Publication date |
2022 |
