| Title |
FPGA IP šerdžių šiuolaikinių kūrimo metodų tyrimas / |
| Translation of Title |
Research of IP cores state-of-art design techniques. |
| Authors |
Šulcas, Mindaugas |
| Full Text |
|
| Pages |
73 |
| Keywords [eng] |
field-programmable gate arrays ; high level synthesis ; intellectual property cores |
| Abstract [eng] |
In this master thesis various intellectual property core design methodologies for field-programmable gate arrays are being analyzed. The goal of this work is to research specific field programmable gate arrays manufacturers recommended tools for core development. The other goal of this work is to create universal intellectual property core benchmarking methodology which would enable digital design engineers to easily select most effective core design tool for specific task solving. The research is carried out by analyzing Xilinx field-programmable gate arrays manufacturers recommended tools for core development and by using these tools to solve most common image processing task – object edge detection. |
| Dissertation Institution |
Kauno technologijos universitetas. |
| Type |
Master thesis |
| Language |
Lithuanian |
| Publication date |
2020 |
