| Title |
Functional delay test construction approaches / |
| Another Title |
Funkcinių vėlinimo gedimų testų konstravimo būdai. |
| Another Title |
Способы конструирования функциональных тестов задержки. |
| Authors |
Bareiša, E ; Jusas, V ; Motiejūnas, K ; Šeinauskas, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2007, Nr. 2, p. 49-54.. ISSN 1392-1215. eISSN 2029-5731 |
| Keywords [eng] |
fault location (engineering) ; electronic circuits ; delay lines |
| Abstract [eng] |
It is explored how functional delay tests constructed at algorithmic level detect transition faults at gate-level. Main attention was paid to investigation of the possibilities to improve the transition fault coverage using n-detection functional delay fault tests. The proposed functional delay test construction approaches allowed achieving 99 % transition fault coverage which is acceptable even for manufacturing test. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2007 |
| CC license |
|
