| Title |
LSFR and BIST based Delay test for ASIC and FPGA / |
| Another Title |
Testinių rinkinių sudarymas vėlinimo gedimams tikrinti save testuojančiose integrinėse schemose, realizuotose ASIC ir FPGA, naudojant postūmio registro su tiesiniu grįžtamuoju ryšiu struktūras. |
| Another Title |
Генерирование тестовых последовательностей для заказных и программируемых интегральных схем со встроенными схемами самотестирования, используя структуры линейного регистра сдвига с обратными связями. |
| Authors |
Abraitis, V ; Tamoševičius, Ž |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2008, Nr. 7, p. 45-48.. ISSN 1392-1215. eISSN 2029-5731 |
| Keywords [eng] |
Delay lines ; electric fault location ; integrated circuits |
| Abstract [eng] |
Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2008 |
| CC license |
|
