| Title |
Combining software and hardware test generation methods to verify VHDL models |
| Another Title |
Programinės ir aparatinės įrangos testų generavimo metodų sujungimas, testuojant VHDL modelius. |
| Authors |
Jusas, Vacius ; Neverdauskas, Tomas |
| DOI |
10.5755/j01.itc.42.4.4261 |
| Full Text |
|
| Is Part of |
Informacinės technologijos ir valdymas = Information technology and control.. Kaunas : KTU. 2013, t. 42, Nr. 4, p. 362-368.. ISSN 1392-124X. eISSN 2335-884X |
| Keywords [eng] |
finite state machines ; control flow graphs ; hardware verification ; test generation |
| Abstract [eng] |
Verification is an important part of the chip design process. Design is usually represented in hardware description language (HDL). Contemporary HDLs have constructs that are characteristic to software programs. Therefore, the methods to automatically generate test for software programs can be applied to generate test for HDL models. One of such methods is symbolic execution. We present a framework to generate test benches for HDL models. The framework combines the methods of symbolic execution and control flow graph, which are usually used in the context of software programs, with finite state machine that is characteristic for HDL models. The framework is implemented in Python programming language. We experimented with ITC’99 benchmark suite and compared the performance of our framework with similar research. Our obtained results outperformed the results taken from similar research. |
| Published |
Kaunas : KTU |
| Type |
Journal article |
| Language |
English |
| Publication date |
2013 |
| CC license |
|
