| Title |
An investigation of possibilities of improving random test generation for non-scan sequential circuits / |
| Another Title |
Nuoseklių schemų atsitiktinio testų generavimo pagerinimo galimybių tyrimas. |
| Authors |
Bareisa, E ; Jusas, V ; Motiejunas, K ; Seinauskas, R |
| DOI |
10.5755/j01.eee.114.8.685 |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : KTU. 2011, Nr. 8, p. 11-15.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. The latest research shows that functional tests designed using random test generation exhibit good transition fault coverages. In the paper, we investigated the possibilities of improving random test generation for at-speed testing of non-scan synchronous sequential circuits. Based on research of distribution of “1” in randomly generated test pattern we suggested guidance for management of test generation process. The implementation of semi deterministic algorithms showed that the optimisation of separate steps by construction of test subsequences doesn’t improve the final outcome. |
| Published |
Kaunas : KTU |
| Type |
Journal article |
| Language |
English |
| Publication date |
2011 |
| CC license |
|
