| Title |
On delay test generation for non-scan sequential circuits at functional level |
| Another Title |
Nuosekliųjų schemų vėlinimo testų generavimas funkciniame lygmenyje. |
| Authors |
Bareisa, E ; Jusas, V ; Motiejunas, K ; Seinauskas, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2011, Nr. 3, p. 67-70.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. We investigated the application of tests that are generated at functional level for detection of gate-level transition faults. Based on experimental results, we developed a framework of delay test generation for non-scan sequential circuits. The provided comparison with experimental results of other approaches demonstrates the effectiveness of proposed framework. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2011 |
| CC license |
|
