Title Nanotechnology problems using VMOS, UMOS /
Another Title Nanotechnologijų problemos formuojant VMOS, UMOS.
Authors Keršys, T ; Andriukaitis, D ; Anilionis, R
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Is Part of Elektronika ir elektrotechnika.. Kaunas : Technologija. 2006, Nr. 6, p. 79-82.. ISSN 1392-1215. eISSN 2029-5731
Abstract [eng] VMOS, UMOS transistors drain and gate are formed in the groove of “V” or “U” form. Channel area is expanded, therefore VMOS and UMOS structures may be used in power chips. Using VMOS, UMOS 40% more free space is saved than using NMOS technology. Nanostructures dimensions are very small, so it is important to keep pn splice at a right depth, during all semiconductor manufacturing technological process. Analyzing influence of each technological operation on structure formation mathematical simulation with program SUPREM IV is used. VMOS and UMOS technological operation was simulated in micro and nano levels.
Published Kaunas : Technologija
Type Journal article
Language English
Publication date 2006
CC license CC license description