| Title |
Etching process simulation in MOS nanoscale structures / |
| Another Title |
Nanomatmenų MOP struktūrų ėsdinimo proceso modeliavimas. |
| Authors |
Andriukaitis, D ; Anilionis, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2006, Nr. 5, p. 9-12.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
Problems of etching process, related with MOS transistors separation in LOCOS and SOS technologies were researched. Wafer of Si selection depending on crystallographic planes orientation is the main task. The etching rate along direct direction and lateral encroachment depends on crystallographic planes orientation. Wet etching is simulated with program ACES. Test photo mask with 100 nm holes for wafer etching is used for etching process simulation. The highest etching rate reached in Si with crystallographic planes orientation (110) – 23 nm/s. The biggest lateral etching belongs to substance with crystallographic planes orientation (100), 17 nm/s on both sides together in wet etching process. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2006 |
| CC license |
|
