| Title |
Juodosios dėžės modelių testų kūrimas / |
| Another Title |
Test design for black-box models. |
| Authors |
Jusas, V ; Paulikas, K ; Šeinauskas, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2005, Nr. 7, p. 35-39.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
Microelectronic circuits are becoming more complex and their testing is more and more complex and expensive. If errors are detected early it is cheaper to correct them. Only high abstraction level models are available at early project stages. High level model is viewed as “black-box” in our research, not looking to its internal design. Algorithms used are based on simulation techniques and are independent of design environment. It is attempted to create test sequence, which be usable in early project stages, and later to adopt it to particular requirements. Experiments show that obtained sequences are shorter than random generated, but have similar test quality. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
Lithuanian |
| Publication date |
2005 |
| CC license |
|
