| Title |
Programuojamosios logikos elemento gedimo modelis / |
| Another Title |
The fault model of programmable logic block. |
| Authors |
Abraitis, V ; Bareiša, E |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2005, Nr. 6, p. 52-56.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
There are presented the fault models of programmable integrated circuits in this paper, when programmable integrated circuits are configured to implement a given application. Proposed fault model can be used with traditionally automatic test sequence generators and result will be exhaustive test for programmable integrated circuits with given configuration. Model was tested using Virtex family PFGA’s. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
Lithuanian |
| Publication date |
2005 |
| CC license |
|
