| Title |
LOCOS proceso taikymas MOS technologijose / |
| Another Title |
Using LOCOS process in a MOS technology. |
| Authors |
Eidukas, D ; Anilionis, R ; Keršys, T |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2005, Nr. 5, p. 38-41.. ISSN 1392-1215. eISSN 2029-5731 |
| Keywords [eng] |
efficiency ; electronic ; system |
| Abstract [eng] |
The problems, appears using LOCOS oxidation technological process in MOS and MNOS technologies have been discussed. Mainly the problems occur then using high temperature technological processes, because starting thermal diffusion of impurities from ion implanted areas. In practice, to determinate the depth changes of pn splice after some technological operation it’s difficult, thus using mathematical simulation. Using program SUPREM IV, mathematical modeling of ion implantation and LOCOS oxide growth has been performed. Anneal of Si wafer and LOCOS process impact to regrouping of diffused areas is estimated. It has been determined that process of LOCOS oxide forming has the most impact to orthogonal deviation of impurity penetration to the depth, than impact to standard deviation of impurity penetration to the depth. This fact it is important to determinate producing high frequency MOS transistors. Just by setting correctly conditions of technological processes, like ion implant dose and energy forming source and drain areas, and temperature and time of LOCOS process, we can obtain necessary location of diffusive layers, and necessary electrical characteristics of MOS elements. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
Lithuanian |
| Publication date |
2005 |
| CC license |
|
