| Title |
Transition fault coverage for different implementations of the circuit / |
| Another Title |
Vėlinimo gedimų apimtis esant įvairioms schemos realizacijoms. |
| Authors |
Bareiša, E ; Jusas, V ; Motiejūnas, K ; Šeinauskas, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2005, Nr. 3, p. 78-83.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. The purpose of this paper is to assist to designer in the decision making how to test transition faults of re-synthesized cores. We have performed various comprehensive experiments with combinational benchmark circuits. Our experiments show that the test sets generated for a particular circuit realization fail to detect in average only less than 1.5% of the transition faults of the re-synthesized circuit but in some cases this figure is more than 9%. The same trends are valid for stuck-at faults of different implementations, too. The double-detection test sets declined almost twice both the maximum and the average percent of undetected transition faults for all implementations of the circuits, except one singular implementation of one circuit. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2005 |
| CC license |
|
