| Title |
The aspects of non-standard CMOS integrated circuits layout design / |
| Another Title |
Nestandartinių KMOP integrinių schemų topologijos projektavimo aspektai. |
| Authors |
Benisevičiūtė, R |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2005, Nr. 2, p. 43-46.. ISSN 1392-1215. eISSN 2029-5731 |
| Abstract [eng] |
The new tendencies of circuit fabrication conditioned the investigation of new design methods. The technology with standardised minimal line width is one from such trends. The possibilities and methodics of design of non-standard cells are presented in the article. The possibilities of insert of non-standard cells layout into common integrated circuit layout are investigated also. The cell layouts from the standard library are interpreted as gates level circuit, because the layouts of those cells are given in the symbolic level. The nonstandard cells are designed in transistor level, so they are interpreted as analogous circuits. The method of simulation of circuits layout with inserted non-standard cells on mixed analogue and logical level is researched. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2005 |
| CC license |
|
