| Title |
Verifiable template development for HDL- descriptions / |
| Another Title |
Verifikuojamų HDL aprašų šablonų kūrimas. |
| Authors |
Syrevitch, Y ; Zinchenko, D |
| Full Text |
|
| Is Part of |
Elektronika ir elektrotechnika.. Kaunas : Technologija. 2007, Nr. 3, p. 49-52.. ISSN 1392-1215. eISSN 2029-5731 |
| Keywords [eng] |
graph theory ; verification (logic) ; adaptive signal processing |
| Abstract [eng] |
Classification of digital devices by types of their language descriptions is introduced. Also, a template of HDL-model of digital device, which will fit verification objectives in a case of using path sensitization methods, is considered. The proposed strategy starts from origin HDL-model transformation into a graph model, which is a composition of two graphs. To identify all functional elements in an informational graph it is necessary and enough to activate all paths in a graph which cover it, starting from the 1st rank to graph outputs or control points. Usage of a template allows building a graph model of HDL-description and further verification easier. Adjustments of path sensitization verification strategy are done. Dependence of test length from the type of testing for S27, КР1804ВС1, and В06 benchmarks is analyze. |
| Published |
Kaunas : Technologija |
| Type |
Journal article |
| Language |
English |
| Publication date |
2007 |
| CC license |
|
