| Abstract [eng] |
Digital image processing devices depend on coding, edge detection and image compression algorithms. The ever increasing demand for image processing in mobile wireless devices it is becoming crucial to ensure not only the quality and speed of these algorithms, but also the problem of power dissipation. One of the most important parts of any image processing algorithm is the discrete cosine transform (DCT) and the inverse discrete cosine transform (IDCT). These transforms are the most complex parts in the coding and decoding process, using up to a quarter of all the mathematical operations in the coding algorithm. The complexity of this system leads to great power dissipation For the increasing number of portable wireless devices, a key design constraint is power dissipation. Limited battery life constrains portable devices to low power dissipation; advances in battery life do not grow as fast as the density and the operating frequency of ASICs [1]. The ever-growing circuit densities and operating frequencies of ASICs only result in greater power dissipation. Therefore it is necessary to find the right algorithm, using the minimum of power, while still providing sufficient coding quality and speed. This thesis focuses on a hardware implementation of DCT and IDCT algorithms. Most popular and practically used algorithms are explored. FPGA gate arrays are used for testing of these algorithms. The main goal is to find the most effective, fastest algorithm with the least power dissipation. Also we focus on the algorithm's suitability for a hardware implementation and the problems of such design. The results display a comparison of the algorithm's speed, coding quality, positive and negative aspects of hardware design. Before the hardware implementations, a mathematical modeling of the algorithms is performed for testing the performance and quality characteristics. |
