| Abstract [eng] |
This work studies arithmetic logic unit (ALU) models, operations and architectures. ALU architecture and operation set is chosen based on the analysis of the known scientific publications. Two-stage divided operation set ALU model is implemented and used for the experiments. The experimental ALU models are modified using different variants of partitioning of ALU operation set, when ALU operations are divided between main ALU block and control unit (CU). Pros and cons of ALU operation performance in the first or the second stage are examined. Developed generic ALU models can be instatiated for data operands with variable data width. ALU models are coded in a high-level hardware description language SystemC, simulated and synthesized. The results of ALU SystemC model synthesis showed the effect of the division of the operation set on the main chip characteristics: area, delay and energy consumption and the difference of subdivision of rare or often used operations into different ALU stages. Optimal subdivision of operation set in two-stage ALU architecture allows getting a better performance of the designed device. Using this method the designer can select an instance of ALU that has a smaller area and consumes less energy for critical (using more hardware resources) operation. |
